Scope Of This Study
A 3D solution at first glance seems an obvious answer to
the interconnect delay problem. Since chip size directly affects the inter
connect delay, therefore by creating a second active layer, the total chip
footprint can be reduced, thus shortening critical inter connects and reducing
their delay. However, in today’s microprocessor, the chip size is not just
limited by the cell size ,but also by how much meta is required to connect the
cells.
Chip area minimization with fixed interconnect delay
Here, VILICs are assumed to consume
negligible area, interconnect line width is assumed to equal half the metal
pitch at all times, and the total number of metal layers for 2-D and 3-D case was conserved. A key
assumption for the geometrical construction of each tier of the multilevel
interconnect network is that all cross sectional dimensions are equal within
that tier.
Effect Of Increasing The Number Of Metal Layers
It is likely that there are local and
semi global tiers associated with every active layer, and a common global tier
is used . This would result in an increase in the total number of metal layers
for the 3-D case. The effect of using 3-D case. The effect of using 3-D ICs
with constant metal layers and the effect of employing twice the number of
metal layers as in 2-D are summarized in the figure.
Thermal Issues In 3d Ics
An extremely important issue in 3-D ICs
is heat dissipation. Thermal effect s are already known to significantly impact
interconnected /device reliability and performance in high-performance 2-D ICs.
The problem is expected to be exacerbated by the reduction in chip size,
assuming that same power generated in a 2-D chip will now be generated in a
smaller 3-D chip, resulting in a sharp increase in the power and density
Analysis of thermal problems in 3-D circuits is therefore necessary to
comprehend the limitations of this technology and also to evaluate the thermal
robustness of different 3-D technology and design options.
Beam Recrystalization
A very popular method of fabricating a
second active layer (Si) on top of an existing substrate (oxidized Si wafer )is
to deposit polysilicon and fabricate thin film transistors (TFT). To enhance
the performance of such transistors ,an intense laser or electron beam is used to induce
recrystalisation of the polysilicon film
to reduce or even eliminate most of the grain boundaries.
Introduction
There is a saying in real estate; when
land get expensive, multi-storied buildings are the alternative solution. We
have a similar situation in the chip industry. For the past thirty years, chip
designers have considered whether building integrated circuits multiple layers
might create cheaper, more powerful chips. Performance of deep-sub micrometer
very large scale integrated (VLSI) circuits is being increasingly dominated by
the interconnects due to increasing wire pitch and increasing die size.
Additionally, heterogeneous integration of different technologies on one single
chip is becoming increasingly desirable, for which planar (2-D) ICs may not be
suitable.
Abstract
The unprecedented growth of
the computer and the Information technology industry is demanding Very
Large Scale Integrated (VLSI) circuits with increasing functionality and
performance at minimum cost and power dissipation. VLSI circuits are being
aggressively scaled to meet this Demand, which in turn has some serious
problems for the semiconductor industry.
Contents
1. Introduction
2. Motivation for 3-D ICs
3. Scope of this study
4. Area and performance estimation of 3-D ICs
5. Challenges for 3-D Integration
6. Overview of 3-D IC technology
7. Present scenario of the 3-D IC industry
8. Advantages of 3-d memory
9. Applications of 3-D ICs
10. Future of 3-D IC industry
11. Conclusion
12. Reference
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